IPClock’s IPC90000 unifies a full IEEE1588v2 (PTPv2) standard compliant Master/Slave Ordinary Clock, Transparent Clock (TC) and Boundary Clock (BC) in a single product.

The IPC90000 flexible architecture is designed to easily integrate in distributed and centralized network device architectures. The IPC90000 is comprised of a Main Card Timing Unit (MCTU) and Line Card Timing Unit (LCTU) elements.  Both the MCTU and LCTU are requiring low CPU and FPGA resources.  The IPC90000 mode of operation can be set according to specific needs supporting combination including Slave OC and TC, Master OC and TC which provides the maximum flexibility to set required functionality on demand.

The IPC90000 main features and benefits include:

• Supports IEEE1588v2 standard compliant Master/Slave OC, E2E/P2P TC and BC modes of operation for distributed and centralized architectures
• Supports up to 16 Line Cards / 24 ports per Line Card
• TC provides accurate resident time and link delay measurements
• Slave phase alignment performance is better than ±1µsec under ITU-T G.8261 conditions
• Fractional frequency offset (FFOFF) performance is better than 15ppb under ITU-T G.8261 conditions
• Controls low-cost analog PLL for supporting Synchronized Ethernet
• End-to-End (E2E) and Peer-to-Peer (P2P) Transparent clock support
• Standard compliant Best Master Clock (BMC) algorithm enables master redundancy
• Upgradeable by software 

The IPC90000 is an excellent choice for applications requiring synchronization icluding:

• Cellular Macro/Micro Cells
• Cellular Pico/Femto Cells
• Cellular backhauling
• WiMAX Base Stations
• Out-of-band clock synchronization for Pseudowire (E1/T1)
• Backup for GPS
• DVB-T broadcast base stations
• DVB-H base stations