IPClock’s IPC70000 is a full IEEE1588v2 (PTPv2) standard compliant Master/Slave Ordinary Clock (OC).

Comprised of innovative Sync over Packet Engine (SoPE), state-of-the-art clock synchronization algorithms suite and IEEE1588v2 protocol stack, the IPC70000 is requiring low CPU power and low FPGA resources.
When in Slave mode, the IPC70000 achieves excellent clock synchronization performance including frequency synchronization, phase and Time of Day (ToD) alignment surmounting stringent packet switched networks (PSN) impairments. When in Master mode, the IPC70000 is serving as a standard compliant low-cost 1588v2 Master solution for applications in need for reducing total cost of ownership with high-performance clock synchronization and minimal overhead. The IPC70000 is designed for easy field upgrades to support future enhancements as well as future clock synchronization standards.

Typical applications include:

• Cellular Macro/Micro Cells
• Cellular Pico/Femto Cells over Ethernet, DSL, Cable, PON
• Cellular backhauling
• WiMAX Base Stations
• Out-of-band clock synchronization for Pseudowire (E1/T1)
• Backup for GPS

The IPC102E Evaluation Kit allows testing the IPC70000 functionality in your network.