Connecting network elements like femto or pico cells over Last-Mile transport technologies like PON, DSL, Cable, or PLC allows the deployment of high-speed networks. The PON, DSL, Cable, or PLC transport layers substantially adds to the inherent packet network impairments to the extent it requires adding sophisticated clock recovery algorithms suit to allow achieving high quality clock recovery.

IPClock’s IPC50005 is a full IEEE1588v2 (PTPv2) standard compliant Slave only Ordinary Clock (OC) comprised of innovative Sync over Packet Engine (SoPE), state-of-the-art clock synchronization algorithms suite and IEEE1588v2 protocol stack. The IPC50005 is requiring low CPU power and low FPGA resources to achieve excellent clock synchronization performance including frequency synchronization, phase and Time of Day (ToD) alignment surmounting stringent packet switched networks (PSN) and last mike technologies impairments.

The IPC50005 is an excellent choice for applications requiring synchronization:

• Cellular Macro/Micro Cells
• Cellular Pico/Femto Cells
• Cellular backhauling
• WiMAX Base Stations

The IPC102E Evaluation Kit allows testing the IPC50005 frequency, phase alignment and time of day synchronization performance in your network.